1.题目
2.源码
// *********************************************************************************// Project Name : Hamming_code// Email : 2972880695@// Website: /u/hqz68/// Create Time : /12/14 // File Name : Hamming_code.v// Module Name : Hamming_code// Abstract:// editor: sublime text 3// *********************************************************************************// Modification History:// Date By Version Change Description// -----------------------------------------------------------------------// /12/14 宏强子 1.0 Original// // *********************************************************************************`timescale1ns/1nsmodule Hamming_code (//system signalsinputsclk, inputs_rst_n,//inputinputstart,input[3:0]data_i,//outputoutputwire[6:0]data_o);//========================================================================\// =========== Define Parameter and Internal signals =========== //========================================================================/localparams0 = 4'd0;localparams1 = 4'd1;localparams2 = 4'd2;localparams3 = 4'd3;reg [3:0]state;reg [6:0]data_reg;reg bit_6;reg bit_5;reg bit_3;//=============================================================================//****************************Main Code *******************************//=============================================================================always @ (posedge sclk or negedge s_rst_n) beginif(s_rst_n == 1'b0)state <= s0;else if (state == s0 & start == 1'b1)state <= s1;else if (state == s1)state <= s2;else if (state == s2)state <= s3;else if (state == s3)state <= s0; elsestate <= state;endalways @ (posedge sclk or negedge s_rst_n) beginif(s_rst_n == 1'b0)data_reg <= 7'd0;else if(state == s1)data_reg <= {1'b0,1'b0,data_i[3],1'b0,data_i[2],data_i[1],data_i[0]};elsedata_reg <= data_reg;endalways @ (state) beginif (state == s1)bit_6 = data_reg[4] ^ data_reg[2] ^ data_reg[1];else if (state == s2)bit_5 = data_reg[4] ^ data_reg[1] ^ data_reg[0];else if (state == s3)bit_3 = data_reg[2] ^ data_reg[1] ^ data_reg[0];else if (state == s0)beginbit_6 = 1'b0;bit_5 = 1'b0;bit_3 = 1'b0;end end assign data_o = (state == s3) ? {bit_6,bit_5,data_reg[4],bit_3,data_reg[2:0]} : 7'd0;endmodule
3.测试平台
`timescale 1ns/1nsmodule tb_sim();regsclk;regs_rst_n;regstart;reg[3:0]data_i;wire[6:0]data_o;initial beginsclk =1;s_rst_n = 0;start = 0;data_i = 4'd0;#100s_rst_n =1;#200start = 1;data_i = 4'b0101; //对应输出 01000101#100start = 0;endalways #50 sclk = ~ sclk;Hamming_code Hamming_code_inst(//system signals.sclk(sclk), .s_rst_n(s_rst_n),//input.start(start),.data_i(data_i),//output.data_o(data_o));endmodule
4.仿真波形
