1. 硬件平台
Cyclone IV 和6个数码管
2. top level
module num_show(input clk,rst,output wire oclk,output [7:0]num_out,output [7:0]n_oled,output [5:0]Cs_out,output wire clk_1M);wire CLK_1M;pllpll_inst (.inclk0 ( clk ),.c0 ( CLK_1M ));flow_ledflow_led(.nclk(clk),.nrst(rst),.out_clk(oclk),.oled(n_oled));num_clock num_clock(.kclk(CLK_1M),.krst(rst),.knum_out(num_out),.kCs_out(Cs_out));endmodule
2. 计时模块
module num_clock(input kclk,krst,output reg [7:0]knum_out,output reg [5:0]kCs_out);reg [20:0]count;reg [3:0] s_num;reg [3:0] s1_num;reg [3:0] m_num;reg [3:0] m1_num;reg [3:0] h_num;reg [3:0] h1_num;reg [2:0] out_select;parameter data = 20'd1000000;//数码管parameter _0 = 8'b0011_1111,_1 = 8'b0000_0110,_2 = 8'b0101_1011,_3 = 8'b0100_1111, _4 = 8'b0110_0110,_5 = 8'b0110_1101,_6 = 8'b0111_1101,_7 = 8'b0000_0111,_8 = 8'b0111_1111,_9 = 8'b0110_1111;//from right leftparameter num_1 = 6'b11_1110,num_2 = 6'b11_1101,num_3 = 6'b11_1011,num_4 = 6'b11_0111,num_5 = 6'b10_1111,num_6 = 6'b01_1111;function [7:0]dataout;input [3:0] in_data;reg [7:0]out_data;begincase (in_data)4'd0: out_data = _0;4'd1: out_data = _1;4'd2: out_data = _2;4'd3: out_data = _3;4'd4: out_data = _4;4'd5: out_data = _5;4'd6: out_data = _6;4'd7: out_data = _7;4'd8: out_data = _8;4'd9: out_data = _9;default: out_data = 8'b1111_1111;endcasedataout = out_data;endendfunctionalways @(posedge kclk or negedge krst)begin if(!krst)beginkCs_out = num_1;out_select <= 1'b1;knum_out <= _0;count <= 0;s_num <= 0;s1_num <= 0; m_num <= 0;m1_num <= 0; h_num <= 0;h1_num <= 0; endelsebegincount <= count + 1'b1; //计时if (count==data)begincount <= 0;//seconds_num = s_num +1'b1;if (s_num == 4'b1010)begins_num = 0;s1_num = s1_num+ 1'b1;if(s1_num==4'b0110)begins_num = 0;s1_num = 0;m_num = m_num +1'b1; //miniif (m_num == 4'b1010)begin m_num = 0;m1_num = m1_num+ 1'b1;if(m1_num==4'b0110)beginm_num = 0;m1_num = 0;h_num = h_num +1'b1; //hourif (h_num == 4'b1010)begin h_num = 0;h1_num = h1_num+ 1'b1;endif(h1_num==4'b0010 && h_num == 4'b0100) //24beginh_num = 0;h1_num = 0;endendendendendend//second//显示刷新率大于20HZif(count % 20'd2500==0)beginout_select=out_select+1'b1;if(out_select==3'b111)out_select=1'b1;case(out_select)3'b001:beginkCs_out = num_1;knum_out = dataout(s_num);end3'b010:beginkCs_out = num_2;knum_out = dataout(s1_num);end3'b011:beginkCs_out = num_3;knum_out = dataout(m_num);end3'b100:beginkCs_out = num_4;knum_out = dataout(m1_num);end3'b101:beginkCs_out = num_5;knum_out = dataout(h_num);end3'b110:beginkCs_out = num_6;knum_out = dataout(h1_num);enddefault: kCs_out = 6'b11_1111;endcaseendendendendmodule
实验代码可根据不同的硬件平台自行修改。
